Color synchronizing signal generating device

ABSTRACT

A SYNCHRONIZING SIGNAL GENERATING DEVICE IN WHICH A 3.58 MHZ BURST SIGNAL IS EXTRACTED FROM AN EXTERNAL NTSC COLOR COMPOSITE SIGNAL WITH A BURST FLAG SIGNAL AND THE BURST SIGNAL OF 3.58 MHZ IS CONTINUOUSLY OSICLLATED. IN THIS CASE, A SIGNAL SEPARATED FROM SYNCHRONIZING SIGNALS IN SYNCHRONIZED RELATIONSHIP IS SUBTRACTED THEREFROM BY THE 3.58 MHZ OF THE BURST SIGNAL, THIS SUBTRACTED SIGNAL IS COUNTED DOWN TO PRODUCE THE VERTICAL SYNCHRONIZING SIGNAL, AND THE SYCHRONIZING SIGNAL IS OBTAINED FROM THE VERTICAL SYNCHRONIZING SIGNAL IN GEN-LOCKED CONDITION.

United States Patent 1191 Kobayashi June 28, 1974 COLOR SYNCHRONIZING SIGNAL Primary ExaminerRichard Murray GENERATING DEVICE A F H G s V Attorney, gent, 0r irm 1 ross, lmpson, an [75] Inventor. itsiirllkazu Kobayaslu, Kawasakl, Santen Steadman, Chiara & Simpson [73] Assignee: Nippon Columbia Kabushikikaisha (Nippon Columbia Co., Ltd.), [57] ABSTRACT Tokyo Japan A synchronizing signal generating device in which a Filedi 1972 3.58 MHz burst signal is extracted from an external NTSC color composite signal with a burst flag signal [21] Appl' 3l2l96 and the burst signal of 3.58 MHz is continuously oscillated. In this case, a signal separated from synchroniz- [52] U S. ;C l, 358/ 11 9,1Z@9.5 CB ing signals in synchronized relationship is subtracted [51] Int. Cl. H04n 9/46 therefrom by the 3,58 MHz of the burst signal, this Field of 695 subtracted signal is counted down to produce the ver- 178/695 CB, G; 1/ 0 tical synchronizing signal, and the synchronizing signal is obtained from the vertical synchronizing signal in [56] References Cited gen-locked condition.

UNITED STATES PATENTS 3,532,810 10/1970 Steinberg..., 178/696 TV 4 Drawmg F'gures ESEtSMEkTFE CLIPPING CIRCUIT Z J :121: 6 14.3 7 FREQUENCY Z# g r/DIVIDER 5Y4 5 3.58 Gossamer 3;; T6- ij 212311 8 2:11. 16 22 Ezigcrms i /Z c1 Rcu1r 3 V 225 cm: 1- mil 3m 1/125 i f i 1 1 1 COUNTER 5 I0 W I 1 x 9 10 HOR. 1 5 .11 g ar f i 1 59 5! iii/i351? 4 10 L 1020 BY rgisouzucv i i /fi i i i IVIDER uuran BY 2 i T8- is I i sanitary m f I 14 1 1 sense: i 1 L 'L i E wea 4 f7 2. SIGNAL 0/ 4/ 11011121111111.

IB HOR.DR|VE i 20% 1 51122 SIGNAL GEN. EEzST HORZANTAL GENERATOR SIGNAL DRIVE SIGNAL 5, 20 9 HOR. PULSE PERIOD PAVENTEBmzs :914 3.821. 788

SfiEET 2 OF 6 VIDEO SIGNAL FREQUENCY MULTIPLIER BURST SIGNAL [-3 Z QUADRUPLER BY 4 CLIPPING Z 2 M 7 FREQUENCY Os MHZ /DlVID/;R BY 4 1 5 3.58 MHz cofig vmso b 358 &

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s BURST FLAG l6 i SIGNAL seu f I SIB :9 20 Z J HORIZONTAL f7 BLANK'NG\ I P HtRlZANTAL SIZNAL lgfi/ W63 204/ PERIOD l8 HOR.DRIVE PULSE SIGNAL GEN. Ell-122T \HORIZANTAL GENERATOR SIGNAL DRHSIE SlGNAL S19 20 ZOR PULISE PERIOD PULSE GEN.

COLOR SYNCHRONIZ ING SIGNAL GETING DEVICE BACKGROUND OF THE INVENTION This invention relates to a color synchronizing signal generating device with which a horizontal drive signal, a horizontal blanking signal, a burst flag signal and so on for use in color television image pickup apparatus are derived from an NTSC color video signal, and more particularly to a color synchronizing signal generating device which is simple in construction and capable of obtaining a color synchronizing signal of accurate phase relation without adjustment.

BRIEF DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to FIG. 2, a description will be given of one example of a color synchronizing signal generating device of this invention.

In FIG. 2, reference numeral 1 indicates an NTSC color video signal input terminal to which is supplied an ordinary NTSC color video signal. The NTSC color video signal supplied to the input terminal 1 is applied to a clipping circuit 2 to be divided into a synchronizing component signal, that is, a signal composed of only vertical and horizontal synchronizing signals and an equalizing pulsesignal and a video component signal, that is, a signal composed of a video signal and a burst signal. The synchronizing component signal is derived at the one output terminal 2a of the clipping circuit 2, while the video component signal is at the other output terminal 2b. The synchronizing component signal thus derived'at the output terminal 20 of the clipping circuit 2 is supplied to a synchronizing signal generator 3 and is thereby shaped in waveform to provide at its output terminal 3a a composite synchronizing signal such as shown in FIG. 4A. In FIG. 4A, reference character VS indicates a vertical synchronizing signal, HS a horizontal synchronizing signal and Eq an equalizing pulse. Further, the composite synchronizing signal derived at the output of the synchronizing signal generator 3 is fed to a burst extracting signal generator 4, in which the phase of the composite synchronizing signal is shifted to provide a burst extracting signal. With the output of the burst extracting signal generator 4, that is, the burst extracting signal, a burst signal is extracted from the video component signal derived at the other output terminal 2b of the clipping circuit 2. The burst signal thus obtained is supplied to an oscillator 5 of about 3.5 8MHz formed with, for example, a quartz oscillator which is provided with an automatic phase control device and stable in oscillation, thus deriving at the output of the oscillator 5 an oscillation signal S of about 358MHz which is coincident in phase with the burst signal contained in the color video signal fed to the input terminal 1. The output signal S from the oscillator 5 is supplied to a frequency quadrupler 6 to derive a signal S of about 14.3MHz at its-output. The output signal S, from the frequency quadrupler 6 is fed to a frequency divider 7 whichdivides by four to provide at its output terminals 7a and 7b respectively subcarrier signals of approximately 3.58MI-Iz which are displaced apart in phase from each other. Further, the composite synchronizing signal S derived from the synchronizing signal generator 3 and the signal S, of about 3.58 MHz from the oscillator 5 are both supplied to a 1/ 128 counter 8 to derive a vertical pulse signal V at its output. The l/ 128 counter 8 is formed with, for example, seven J-K flip-flop circuits 8a, 8b, 8c, and 8g as shown in FIG. 3. The signal 8;, of about 3.58MHz is supplied to a' trigger terminal T of the first J-K flipflop circuit 8a, the output terminal Q of which is connected to the trigger terminal T of the second J-K flip-flop circuit8b, the output terminal Q of which is, in turn, connected to the trigger terminal T of the third J-K flipflop circuit 8c. In a similar manner, the output terminals Q of the third, fourth, fifth and sixth J-K flip-flop circuits 8c, 8d, 8e and 8f are sequentially connected to the trigger terminals T of the fourth, fifth, sixth and seventh J-K flip-flop circuits 8d, 8e, 8f and 8g respectively. Reference numeral 8h designates an inverter circuit, whose input terminal 8h is supplied with the composite synchronizing signal S such as depicted in FIG. 4A. The output from the inverter circuit 811 is applied to reset terminals R of the MC flip-flop circuits 8a, 8b, 8c, and 8g respectively and signals such as shown in FIGS. 48 and 4C which are derived at the output terminals Q of the J-K flip-flop circuits 8f and 8g are supplied to the input side of a NAND circuit 81' to derive at its output terminal 81}; a vertical pulse signal V such as depicted in FIG. 4D. Reference numeral 9 indicates a frequency divider which divides by 455, which is supplied with theoutput from the frequency quadrupler 6, that is, the signal S, of approximately 14.3MI-Iz and the vertical pulse signal V derived from the l/128 counter 8, thereby providing at the output of the frequency divider 9 a l/2 horizontal pulse S which is synchronized with the leading edge of the vertical synchronizing signal VS. The frequency divider 9 is formed with, for example, nine J-K flip-flop circuits 9a,

9b, 9c, and 9i as illustrated in FIG. 5. The output from the frequency quadrupler 6, that is, the signal S of about 14.3MHz is supplied to the trigger terminal T of the first flip-flop circuit 9a, the output terminal Q of which is connected to the trigger terminal T of the second .I-K flip-flop circuit 9b, the output terminal Q of which is, in turn, connected to the trigger terminal T of the third J-K flip-flop circuit 9c. In a like manner, the output terminals Q of the subsequent third, fourth, fifth, six, seventh and eighth J-K flip-flop circuits 9c, 9d, 9e, 9f, 9g and 9h are sequentially connected to the trigger terminals T of the fourth, fifth, sixth, seventh, eighth and nine J-K flip-flop circuits 9d, 9e, 9f, 9g, 9h and 91 respectively. The output terminals Q of the J-K flip-flop circuits 9a, 9b, 90, 93, 9h and 91' are connected to the input side of NAND circuit 9j and the output terminal of the NAND circuit 9j and that of the 1/l28 counter 8 are connected to the input side of a NOR circuit 9k, the output terminal of which is connected a is supplied with the output from the frequency quadrupler 6, that is, the signal of about 143MHz and the output signal 8,; from the frequency divider 9, thus deriving at the output of the frequency 10 a clock pulse S of about 7. l6MHz such as shown in FIG. 7A which is l/2 the output of the frequency quadrupler 6 and'synchronized with the output signal S The frequency divider 10 is such a J-K flip-flop circuit as depicted in FIG. 6. The output signal of I about 14.3 MHz from the frequency quadrupler 6 is applied to the trigger terminal T of the J-K flip-flop circuit and the output signal 8,, of the I/455 frequency divider 9 is supplied to its reset terminal R to provide at its output terminal a clock pulse S of approximately 7. l6 MI-Iz such as shown in FIG. 7A. The clock pulse S thus derived at the output of the frequency divider I0 is fed to a l/l28 counter 11. The 1/ l 28 counter 11 is formed with seven J-K flipflop circuits 11a, 11b, 11c, and 11g as illustrated inFlG. 8. The output signal S from the frequency divider 10 is applied to the trigger terminal T of the first .l-K flip-flop circuit 110, the output terminal Q of which is connected to the trigger terminal T of the second .l-K

- flip-flop circuit 11b, the output terminal Q of which is,

in turn, connected to the trigger terminal T of the third J-K flip-flop circuit llc. Likewise, the output terminals 0 of the subsequent third, fourth, fifth and sixth J-K flip-flop circuits 11c, 11d, lle and 11 f are sequentially connected to the trigger terminals T of the fourth, fifth, sixth and seventh .I-K flip-flop circuits 1 1d, 1 1e, 1 1 f and 1 lg respectively. The output signal 5 from the frequency divider 9 is supplied to reset terminals R of the .l-K flip-flop circuits 11a, 11b, 11c, and 11g respectively, the outputterminals Q of which are connected to output terminals lla 1112 110 and 113 respectively. In this case, a clock pulse of about 3.58MHz such as depicted in FIG. 7B is derived at the output terminal 1 If the frequency of the logic pulse obtained at the output terminal lla is taken as S, output signals derived at the output terminals 11b llc lld lle llf and llg are logic pulses such as shown in FIGS. 7C, D, E, F, G and H which have frequencies U28, U45, U85, l/l6S, 1/32S and l/64S respectively. The symbols of these logic pulses will hereinafter be referred to as S, U28, U45, U88, U168, H328 and H648. Further, the output signal S from the synchronizing signal generator 3, the output signal 5 of the frequency divider 9, the clock pulse signal S from the frequency divider 10 and the logic pulses, S, 112$, U45, U88, 1/168, 11328 and H648 from the l/l28 counter 11 are supplied to a pulse shaping circuit 12 respectively. The pulse shaping circuit 12 comprises a U2 horizontal pulse generator 13 formed with a logic circuit for generating a l/2 horizontal pulse synchronized with the leading edge of the horizontal synchronizing signal, a horizontal pulse generator 14,. 211/514 counter '14, a 9-horizontal-period pulse generator 16, a 21-horizontal-period pulse generator 17, a horizontal blanking signal generator 18, a burst flag signal generator 19 and a horizontal drive signal generator 20. The 1/2.horizontal pulse generator 13 is formed with one J-K flip-flop circuit 13a as depicted in FIG. 9. The logic pulse 1/64S is supplied to its trigger terminal T and the output from a NOR circuit 13b, the input side of which is supplied with the vertical pulse signal V and the output signal S, from the frequency divider 9, is supplied to a K terminal of the circuit-13a to derive at its output terminal Q a U2 horizontal pulse signal S synchronized with the leading edge of the horizontal synchronizing signal. The 1/514 counter is formed with ten .l-K flip-flop circuits 15a, 15b, 15c, and ISj as shown in FIG. 10. The output signal 8,; from the 1/2 horizontal pulse generator 13 such as depicted in FIG. 11B is supplied to the trigger terminal T of the I first .l-K flip-flop circuit 150, the output tenninal Q of which is connected to the trigger terminal T of the second .I-K flip-flop circuit 151), the output terminal 0 of which is, in turn, connected to the trigger terminal T of the third .l-K flip-flop circuit 150. Similarly. the output terminals 0 of the third to ninth .l-K flip-flop circuits 15c to lSi are sequentially connected to the trigger terminals T of the fourth to tenth J-K flip-flop circuits 15d to 15j respectively. The output terminals of the .l-K flip-flop circuits 15b and 15] are connected to the input side of a NAND circuit 15!: respectively and the output terminal of NAND circuit 151: and that of the N128 counter 8 at which the vertical pulse signal V is ob tained are connected to the input side of a NOR circuit 151, the output terminal of which is connected to the input side of an inverter circuit 15m to provide at its output terminal such a signal as shown in FIG. 11C. The output signal derived at the output terminal of the inverter circuit 15m is applied to reset terminals of the J-K flip-flop circuits 15a to 15 respectively to obtain at the output terminal of the 1/514 counter 15 a pulse signal S such as depicted in FIG. 11D which is synchronized with the trailing edge of the vertical drive signal. FIG. 11A illustrates a composite synchronizing signal. The 9-horizontal-period pulse generator 16 is formed with two' J-K flip-flop circuits 16a and 16b as illustrated in FIG. 12. The U2 horizontal pulse signal S such as shown in FIG. 13A is applied to the trigger terminals T of the J -K flip-flop circuits 16a and 16b and the output signal S such as depicted in FIG. 138 which is derived from the 1/514 counter 15 is fed to a K terminal of the J-K flip-flop circuit 16a. A signal such as shown in FIG. 13C, which is produced by supplying an AND circuit with signals derived at the output terminals Q of the J-K flip-flop circuitsv 15b and 15c of the 1/514 counter 15, is applied to .l termina ls of the .l-K flip-flop circuits 16a and 16b and a signal 8,, produced by reversing the phase of the output signal S is supplied to the reset terminal R of the J-K flip-flop circuit 16a and the input side of a NAND circuit 16c. Further, a signal such as depicted in FIG. 13D, which is derived at a NOT output terminal Q of the J-K flip-flop circuit 16a, is applied to the input side of the NAND circuit 16c and a signal such as shown in FIG. 13E, which is obtained at the output of the NAND circuit 160, is supplied to the reset terminal R of the J-K flip-flop circuit 16b and the K terminal of the J-K flip-flop circuit 16b is grounded. Thus, a 9-horizontal-period pulse signal, that is, a vertical drive signal S such as illustrateg in FIG. 13F is derived at the NOT output terminal Q of the .l-K flip-flop circuit 16b, that is, at the output terminal 16 of the 9-horizontal-period pulse generator 16. The horizontal pulse signal generator 14 is formed with one .I-K flip-flop circuit 14a as shown in FIG. 14, the

trigger terminal T of which is supplied with the l/ 2 horizontal pulse signal S 13 and the reset terminal R of which is supplied with the output of a NAND circuit 14b supplied at its input side with the composite synchronizing signal S and the 9-horizontal-period pulse signal S thus providing a horizontal pulse signal S at the output terminal of the horizontal pulse signal generator 14, that is, the output terminal Q of the J-K flipflop circuit 14a. The 2l-horizontal-period pulse generator 17, the horizontal blanking signal generator 18, the burst flag signal generator 19 and the horizontal drive signal generator 20 are also formed with logic circuits respectively. The 2l-horizontal-period pulse generator 17 is supplied with the output signal S from the 1/514 counter 15 to derive a 21-horizontal-period pulse signal S at its output. The horizontal blanking signal generator 18 is supplied with the output signal S from the frequency divider 10, the logic pulse from the l/l28 counter 11, the output signal S from the horizontal pulse generator 14 and the output signal S from the 2l-horizontal-period pulse generator 17, at an output terminal 18a of the horizontal blanking signal generator 18 a horizontal blanking signal S as shown in FIG. 1B. The burst flag signal generator 19 is supplied with the output signal S from the frequency divider 10, the logic pulse from the l/ l 28 counter ll 1, the output signal S from the horizontal blanking signal generator 18 and the output signal from the 9-horizontal-period pulse generator 16, thereby to provide at an output terminal 190 of the burst flag signal generator 19 such a burst flag signal S as depicted in FIG. 1C. Further, the horizontal drive signal generator 20 is supplied with the output signal S from the frequency divider 10, the logic pulse from the l/l28 counter 11 and the output signal S from the horizontal drive pulse generator 14 to obtained at an output terminal 200 of the horizontal drive signal generator 20 a horizontal drive signal S such as shown in FIG. 1A.

With the present invention, it is possible to obtain from an NTSC color video signal being broadcast the composite synchronizing signal S a subcarrier signal, the vertical drive signal S the horizontal blanking signal S the burst flag signal S and the horizontal drive signal 8 which are necessary for color television image pickup apparatus.

Since the present invention is designed to obtain the color synchronizing signal only with logic circuits as described in the foregoing, color signals of accurate phase relationship can be obtained without involving any adjustment. Further, the device of the present invention does not employ any capacitors and coils, and hence is extremely suitable for fabrication as an integrated circuit. Moreover, the device of this invention is formed with logic circuits, without using an integrator circuit, a one-shot multivibrator and so on which are unstable with respect to temperature, so that the temperature characteristic of this device is dependent upon that of the logic circuit and is extremely stable.

It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.

1 claim as my invention:

1. A color synchronizing signal generating device comprising a clipping circuit supplied with an N'lSC color video signal, a synchronizing signal generator supplied with a synchronizing component signal de rived at a first output of said clipping circuit to provide 6 a synchronizing signal, a burst signal extracting signal generator for generating a burst extracting signal receiving an input from said synchronizing signal generator, an oscillator supplied with a video component signal derived from a second output of said clipping circuit and receiving an input from said burst extracting signal generator to produce a signal of about 3.58MH2 synchronized with a burst signal contained in the video signal, a frequency quadrupler receiving the output of said oscillator and multiplying the frequency by four. a l/ l 28 counter receiving the output of said synchronizing signal generator and an output of about 3.58MHz from said oscillator to produce a vertical pulse signal. a frequency divider by 455 receiving the output of said frequency quadrupler and receiving an input from said l/ 128.counter, a frequency divider dividing frequency by two receiving an output of said frequencyquadrupler and dividing down to l/2 and receiving an input from said frequency divider dividing by 455, a second 1/ l 28 counter receiving output from said frequency divider by two to derive a logic pulse at its output, and

a pulse shaping and generator circuit formed with logic circuits receiving the output from said frequency divider, dividing by 455, the output from said second frequency divider by two and the logic pulse from said 1/ 128 counter to derive horizontal and vertical drive signals, a blanking signal, and a burst flag signal at its outputs.

2. A color synchronizing signal generating device according to claim 1 wherein said pulse shaping generator includes, a horizontal blanking signal generator producing a horizontal blanking signal receiving outputs from said frequency divider by two and said second l/ 128 counter, a horizontal pulse generator receiving an input fromv said synchronizing signal generator and supplying an input to said horizontal blanking signal generator, a 1/2 horizontal pulse generator receiving an input from said second 1/128 counter and said frequency divider by 455 and supplying an input to said horizontal pulse generator, a l/5l4 counter receiving an input from said l/2 horizontal pulse generator, a 9 horizontal pulse period generator receiving the output of said 3/514 counter, and supplying an input to said horizontal pulse generator, and a 21 horizontal period pulse generator receiving an input from said l/5l4 counter and supplying an input to said horizontal blanking signal generator.

3. A color synchronizing signal generator according to claim 2 including a burst flag signal generator producing a burst flag signal and receiving inputs from said frequency divider by two, said second I/ 128 counter, said horizontal blanking signal generator and said 9 horizontal pulse period generator.

4. A color synchronizing signal generator according to claim 3 including a horizontal drive signal generator producing a horizontal drive signal and receiving inputs from said horizontal pulse generator, said second 1/128 counter, and said frequency divider by two.

5. A color synchronizing signal generating device comprising:

a. a clipping circuit supplied with an NTSC color video signal; I

h. a synchronizing signal generator connected to the clipping circuit and receiving a synchronizing component signal derived at a video signal output of the clipping circuit to provide a synchronizing signal;

c. a burst signal extracting signal generator connected to the synchronizing signal generator for generating a burst extracting signal synchronized with the synchronizing signal derived from the synchronizing signal generator;

d. an oscillator connected to said clipping circuit and said burst signal extracting signal generator and supplied with a video component signal derived at a synchronizing signal output of said clipping circuit and said burst extracting signal derived from said burst extracting signal generator to produce a signal of about 358MHz synchronized with a burst signal contained in the video signal;

e. a frequency quadrupler connected to said oscillator and quadrupling the output from the oscillator;

f. A 1/128 counter supplied with the output from the synchronizing signal generator and the output of about 3.58MH2 from said oscillator to obtain a vertical pulse signal;

g. a frequency divider dividing by 455 for frequency receiving the output of the frequency quadrupler to divide it in synchronism with the output from the 1/128 counter;

h. a frequency divider dividing by two receiving the output of the frequency quadrupler to divide it in synchronism with the output from the frequency divider by 455;

i. a 1/128 counter supplied with the output from the frequency divider by two to derive a logic pulse at its output; and

j. a pulse generator circuit formed with logic circuits supplied with the output from the frequency divider by 455 the output from the frequency divider by two and the logic pulse to derive horizontal and vertical drive signals, a blanking signal and a burst flag signal at the output of said pulse generator circuit. 

